AMD announced more than $10 billion in investments across Taiwan’s semiconductor ecosystem on Thursday, targeting advanced chip packaging and manufacturing partnerships needed to support its next-generation AI infrastructure.
The investments center on expanding capabilities in 2.5D chip interconnect packaging technology, which links chips together to improve performance and power efficiency, the company said
AMD is collaborating with Taiwan-based packaging and testing firms ASE and its unit SPIL to develop and qualify what it calls Elevated Fanout Bridge, or EFB, technology. That technology will support AMD’s sixth-generation EPYC processors, codenamed “Venice,” according to AMD. The company said it also reached a milestone with Taiwanese firm PTI by qualifying the first 2.5D panel-based EFB interconnect.
The announcement extends to the deployment of AMD’s Helios rack-scale AI server platform, which the company said is on track for production in the second half of 2026. Manufacturing partners for Helios include Sanmina, Wiwynn, Wistron, and Inventec. The platform pairs AMD Instinct MI450X GPUs with Venice CPUs and runs on AMD’s ROCm open software stack, the company said. “As AI adoption accelerates, our global customers are rapidly scaling AI infrastructure to meet growing compute demand,” AMD Chair and CEO Lisa Su said in a statement. “By combining AMD leadership in high-performance computing with the Taiwan ecosystem and our strategic global partners, we are enabling integrated, rack-scale AI infrastructure that helps customers accelerate deployment of next-generation AI systems.” TSMC’s cutting-edge 2-nanometer fabrication process is being used to manufacture the Venice CPUs, Reuters reported.