The new semiconductor design doubles transistor density and boosts performance by up to 50% over IBM’s 2 nm chips.
IBM introduced a sub-1 nanometer chip architecture featuring 100 billion transistors on a fingernail-sized chip, marking a major advance in semiconductor scaling. The design uses a 3D “nanostack” approach to vertically layer transistors, doubling density compared to IBM’s current 2 nm technology.
The new architecture promises up to 50% higher performance or 70% better energy efficiency, targeting generative AI, cloud infrastructure, and next-gen electronics. IBM also reported a 40% scaling improvement in SRAM, enabling more efficient processors for AI workloads.
Analysts view the development as a long-term strategic move to strengthen IBM’s position in advanced semiconductor and AI hardware markets.